This disclosure concerns improving the propagation speed and pulse shape of digital signals propagating in an integrated circuit laid out such that successive loads are located at incremental distances down a signal line coupled at a near end to a signal source. Such a configuration is exemplified by the addressing and enable signals that address or select bit cells in an integrated circuit memory such as a static random access memory (SRAM). Loads that are more distant down the line from the source are electrically isolated from the nearer loads by a gap provided along the signal line, forming two or more discrete subsets of the loads. The signal line is configured with two or more conductors, one being a fly-over conductor that bypasses the nearer loads and couples the more distant loads to the signal source or to a point more proximal to the source.
Integrated circuits may have a succession of load devices connected commonly to a same signal line. The signal line comprises a conductive path over which a signal propagates from a source, down the line to each load in turn. In a digital device, the signal is typically a square pulse or a rising or falling transition in voltage level representing a changing logic value.
A array of bit cells in an integrated circuit memory, has word lines and bit lines that extend across the span of the array and are coupled to numerous bit cells along the rows and columns that correspond in location. Additionally, address gates for enabling selected rows and columns are located along perimeters of the array. An integrated circuit SRAM is one example. Various other digital devices and configurations also may be characterized by load devices located one after another down the line along the same conductor carrying a signal to the loads. The loads are functionally coupled in parallel with one another but physically are successively located along the signal line, spaced by legs of the signal-carrying conductor running between adjacent load devices.
It is possible in some configurations that one gate output or inverter or line driver or other device functioning as a single signal source may be used directly to drive all of the load device inputs along the conductor. But in other configurations, the loads may be numerous and the signal line long; or the conductor coupling the signal source to the loads may have considerable electrical resistance; or the conductor or the loads may be characterized by considerable capacitance; or it may be desired to operate with a very high frequency and short signal pulse width. Any or all of these conditions can be such that a single line driver or gate output is not sufficient to drive all of the loads.
Applicable load devices may include, for example, actively switched circuit elements such as transistors, inverters, gates, latches, flip-flops and the like. The input signals are typically clocking or switching signals and also level or data signals that need to achieve a predetermined logic level as of some point in time. Insofar as the inputs the devices are semiconductors, capacitance is associated with the gates of CMOS field effect transistors (FETs) or the bases or emitters of bipolar transistors in gates. The maximum operational frequency of circuits containing such load devices may be limited by the delay needed to establish necessary levels and to apply necessary clocking edges, dependably, at the remotest and/or slowest of the switched circuit elements.
A typical six-transistor (6T) bit cell used for CMOS SRAM has two cross-coupled inverters, each comprising a complementary NMOS and PMOS transistor pair. Because the inverters are cross coupled (inputs to outputs), they hold one another in stable logic state until forced to switch, whereupon the inverters hold one another in the other logic state. The bit cell thus stores one bit of information that can be read or written. Access for read or write operations is through two NMOS FET isolation transistors known as passing gates, coupled to the inverter cross coupling nodes on both sides of the cell. The two passing gates respectively connect the cell to a bit line signal BL and a bit line complement signal BLB. (The bit line complement BLB may alternatively be identified as BL-Bar or BLN or BL-not, etc.)
So long as the power remains on the bit cell, the bit cell is stable because the two inverters hold one another in their present state. The isolation transistors allow the bit cell to float when its word line is not asserted, and protect the value stored in the cell during pre-charging of the bit line signals. The values of the bit line signals BL and BLB determine whether the cell is to be read or written. After precharging of the bit line signals, a pulse on the word line control signal WL switches the passing gate transistors into a conductive state, thus accessing the cell for reading or writing according to the bit line values. External tri-state drivers are used to determine the bit cell value when reading, and when writing to the bit cell, to force the inverters to change state as necessary.
An SRAM is typically constructed in a regular row-and-column grid layout of one bit memory cells. An individual bit cell is addressed by applying a word line (WL) signal to address and enable all the bit cells along a given line, and then applying a combination of values to two complementary bit lines (BL and BLB) to read from or to write to the cells that correspond to the bit positions in the word. When the word line signal for a particular bit cell is not selected, the cells on that word line are isolated.
In a typical configuration associated with addressing the bit cells of an SRAM, inputs that define a binary number word line address are decoded to one word line, enabled at the input of a gate for that word line, and the other input of the gate is coupled to a clocking pulse. The output of the gate can be coupled to an inverter that functions as a line driver to apply the clocking pulse to the loads on the addressed word line, namely the gates of the passing gate transistors for all the bit cells on the word line. A situation may occur in which the word line is sufficiently long that the slew rate on the rising and falling edges of the pulse at the farthest bit cell is poor. Or the pulse may not achieve a full swing between respective logic states at the farthest bit. A conventional solution to this problem is to insert a repeater along the signal path to improve the signal slew for the distant elements. The repeater comprises two inverters in cascade (two being necessary to maintain the high-true or low-true logic sense of the signal). The repeater drives the signal to the more distant elements, but each inverter adds an additional propagation delay. Each inverter occupies valuable circuit area.
For purposes of illustration and without limitation, the handling of signals applied to loads as described is exemplified in this disclosure by static random access memory (SRAM) bit cells, their line addressing gates and bit cell line drivers. A memory array on an integrated circuit may have tens of thousands of bit cells disposed typically in a regular X-Y grid arrangement in which word lines and bit lines respectively address rows and columns. The intersection of a word line (WL) selected by a pulsed signal, and bit lines (BL and BLB) selected by logic levels, causes writing or reading to or from the bit cell.
An SRAM arrangement could comprise, for example, 128 word line rows, each row having 256 bit lines. Each of the 128 word line signals may be selected by a word line enable gate, all the word line enable gates being loads along a signal path. Likewise, the word lines are coupled to the gate terminals of two NMOS FETs that function as passing gates to couple the bit lines (BL and BLB) to the normally-floating cross-coupled inverters of bit cells when the associated word line signal is asserted, in this example totaling 512 NMOS FET transistors successively coupled along the word line signal path.
The loads as described that are placed along the signal lines each contribute a capacitance. Each leg of the signal conductor extending between the successive loads inserts a resistance. Each iteration of a series resistance and parallel capacitance along the signal path functions as a low pass filter, from the load device closest to the signal source out to the load device farthest from the signal source. As a result, each load sees a progressively more filtered version of the word line signal. If the original signal is a pulse with square edges between levels equal to the power supply voltages, the rise and fall times of the pulse and the full swing between logic level voltages deteriorate from each load to the next. The time at which the edges of the pulse cross the threshold voltage of the NMOS FETs becomes later at each successive load and the amplitude of the swing is attenuated.
It is known when driving a long signal line characterized by attenuation to boost the amplitude of the signal by inserting repeaters at spaced locations, i.e., line driving amplifiers. In a digital embodiment, the line driver can comprise a digital inverter, or more typically, two cascaded inverters so that the same logic level polarity is maintained. The output of such a line driver is squared up. The output has a short rise time. The output swings between the high and low power supply voltages. However, the line driver inserts a propagation delay even in addition to the propagation delay resulting from the serial resistance of the signal conductor and the capacitance of the loads. Furthermore, space in the integrated circuit is needed for two cascaded inverters forming a line driver (at least four MOS transistors) and such space would be required for each of the lines that requires a line driver. It would be advantageous is a solution could be provided that uses less circuit area, is less complicated and does not introduce unnecessary propagation delay.
Propagation delay and signal attenuation associated with the resistance of conductors carrying a signal from one load device to the next, are increasingly important issues as the scale of integrated circuits is made smaller and smaller. The new 28 nm integrated circuit technology processes of Taiwan Semiconductor Manufacturing Corp. (TSMC), for example, delivers twice the gate density of a 40 nm process, and has a 50 percent smaller SRAM bit cell size. But if the conductors used to carry signals are narrower and thinner than in previous technologies, the resistance per unit length is increased (in this case substantially doubled). If the SRAM cells are smaller, they are also more densely positioned. In small scaled high density configurations, the combined serial resistance of conductor legs between loads and the characteristic FET gate capacitance of the SRAM transistors produces propagation delay and signal attenuation that remains an issue even though the nominal length of a conductor needed to serve a given number of successive loads is scaled down.
It would be advantageous to provide a circuit and technique that enables driving a long line of load devices from a signal conductor or a densely loaded signal conductor generally with closer spaced loads between conductor legs of greater resistance, while minimizing propagation delay and its associated challenges.